ARM Cortex-A76 Core User Manual

A1.7 Product revisions
This section indicates the first release and, in subsequent releases, describes the differences in
functionality between product revisions.
r0p0
First release.
r1p0
Further development and optimization of the product, including updates to the L2 data RAM
control inputs to allow multi-cycle hold timing constraints to ease timing closure.
r2p0
Includes Inter-Exception level isolation of branch predictor structures so that an Exception
Level cannot train branch prediction for a different Exception Level to reliability hit in these
trained prediction entries. Implemented new barrier SSBB.
r3p0
Implemented new barriers PSSBB and CSDB. Support for Speculative Store Bypass Safe
(SSBS) bit enabling software to indicate whether hardware is permitted to load or store
speculatively.
A1 Introduction
A1.7 Product revisions
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A1-32
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core