A8.5 Error Synchronization Barrier
The Error Synchronization Barrier (ESB) instruction synchronizes unrecoverable system errors.
In the Cortex-A76 core, the ESB instruction allows efficient isolation of errors:
• The ESB instruction does not wait for completion of accesses that cannot generate an asynchronous
external abort. For example, if all external aborts are handled synchronously or it is known that no
such accesses are outstanding.
• The ESB instruction does not order accesses and does not guarantee a pipeline flush.
All system errors must be synchronized by an ESB instruction, which guarantees the following:
• All system errors that are generated before the ESB instruction have pended a System Error Interrupts
(SEI) exception.
• If a physical SEI is pended by or was pending before the ESB instruction executes, then:
— It is taken before completion of the ESB instruction, if the physical SEI exception is unmasked at
the current Exception level.
— The pending SEI is cleared, the SEI status is recorded in DISR_EL1, and DISR_EL1.A is set to 1
if the physical SEI exception is masked at the current Exception level. It indicates that the SEI
exception was generated before the ESB instruction by instructions that occur in program order.
• If a virtual SEI is pended by or was pending before the ESB instruction executes, then:
— It is taken before completion of the ESB instruction, if the virtual SEI exception is unmasked.
— The pending virtual SEI is cleared and the SEI status is recorded in VDISR_EL2 using the
information provided by software in VSESR_EL2, if the virtual SEI exception is masked.
After the ESB instruction, one of the following scenarios occurs:
• SEIs pended by errors are taken and their status is recorded in ESR_ELn.
• SEIs pended by errors are deferred and their status is recorded in DISR_EL1 or VDISR_EL2.
This includes unrecoverable SEIs that are generated by instructions, translation table walks, and
instruction fetches on the same core.
Note
DISR_EL1 can only be accessed at EL1 and above. If EL2 is implemented and HCR_EL2.AMO is set to
1, then reads and writes of DISR_EL1 at Non-secure EL1 access VDISR_EL2.
See the following registers:
• B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 on page B2-194.
• B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212.
• B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 on page B2-286.
A8 Reliability, Availability, and Serviceability (RAS)
A8.5 Error Synchronization Barrier
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A8-107
Non-Confidential
To Next Page
Loading...
Need help?
General
