ARM Cortex-A76 Core

D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
The PMPIDR3 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMPIDR3 is a 32-bit register.
31 0
34
CMOD
78
REVAND
RES0
Figure D6-9 PMPIDR3 bit assignments
RES0, [31:8]
RES0 Reserved.
REVAND, [7:4]
0x0 Part minor revision.
CMOD, [3:0]
0x0 Customer modified.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC.
D6 Memory-mapped PMU registers
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
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