B2.95 TCR_EL3, Translation Control Register, EL3
The TCR_EL3 controls translation table walks required for stage 1 translation of memory accesses from
EL3 and holds cacheability and shareability information for the accesses.
Bit field descriptions
TCR_EL3 is a 32-bit register and is part of the Virtual memory control registers functional group.
31 30 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5
0
SH0TG0PS0
IRGN0
ORGN0
T0SZ
TBI
29 28 25
HA
HD
HPD
RES0
RES1
27 26
HWU59
HWU60
HWU61
HWU62
Figure B2-79 TCR_EL3 bit assignments
Note
Bits[28:21], architecturally defined, are implemented in the core.
HD, [22]
Dirty bit update. The possible values are:
0 Dirty bit update is disabled.
1 Dirty bit update is enabled.
HA, [21]
Stage 1 Access flag update. The possible values are:
0 Stage 1 Access flag update is enabled.
1 Stage 1 Access flag update is disabled.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.95 TCR_EL3, Translation Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-280
Non-Confidential
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