D9.48 TRCLSR, Software Lock Status Register
The TRCLSR determines whether the software lock is implemented, and indicates the current status of
the software lock.
Bit field descriptions
The TRCLSR is a 32-bit register.
31 1 0
SLK
2
SLI
3
nTT
RES0
Figure D9-46 TRCLSR bit assignments
RES0, [31:3]
RES0 Reserved.
nTT, [2]
Indicates size of TRCLAR:
0 TRCLAR is always 32 bits.
SLK, [1]
Software lock status:
0 Software lock is clear.
1 Software lock is set.
SLI, [0]
Indicates whether the software lock is implemented on this interface.
1 Software lock is implemented on this interface.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCLSR can be accessed through the external debug interface, offset 0xFB4.
D9 ETM registers
D9.48 TRCLSR, Software Lock Status Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-558
Non-Confidential
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