ARM Cortex-A76 Core User Manual

D9.48 TRCLSR, Software Lock Status Register
The TRCLSR determines whether the software lock is implemented, and indicates the current status of
the software lock.
Bit field descriptions
The TRCLSR is a 32-bit register.
31 1 0
SLK
2
SLI
3
nTT
RES0
Figure D9-46 TRCLSR bit assignments
RES0, [31:3]
RES0 Reserved.
nTT, [2]
Indicates size of TRCLAR:
0 TRCLAR is always 32 bits.
SLK, [1]
Software lock status:
0 Software lock is clear.
1 Software lock is set.
SLI, [0]
Indicates whether the software lock is implemented on this interface.
1 Software lock is implemented on this interface.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCLSR can be accessed through the external debug interface, offset 0xFB4.
D9 ETM registers
D9.48 TRCLSR, Software Lock Status Register
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D9-558
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core