ARM Cortex-A76 Core

Table D2-1 AArch64 debug register summary (continued)
Name Type Reset Width Description
DBGBVR5_EL1 RW - 64 Debug Breakpoint Value Register 5
DBGBCR5_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
OSECCR_EL1 RW
0x00000000
32 Debug OS Lock Exception Catch Register
MDCCSR_EL0 RO
0x00000000
32 Monitor Debug Comms Channel Status Register
DBGDTR_EL0 RW
0x00000000
64 Debug Data Transfer Register, half-duplex
DBGDTRTX_EL0 WO
0x00000000
32 Debug Data Transfer Register, Transmit, Internal View
DBGDTRRX_EL0 RO
0x00000000
32 Debug Data Transfer Register, Receive, Internal View
MDRAR_EL1 RO
-
64 Debug ROM Address Register. This register is reserved, RES0
OSLAR_EL1 WO - 32 Debug OS Lock Access Register
OSLSR_EL1 RO
0x0000000A
32 Debug OS Lock Status Register
OSDLR_EL1 RW
0x00000000
32 Debug OS Double Lock Register
DBGPRCR_EL1 RW - 32 Debug Power/Reset Control Register
DBGCLAIMSET_EL1 RW
0x000000FF
32 D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
on page D2-411
DBGCLAIMCLR_EL1 RW
0x00000000
32 Debug Claim Tag Clear Register
DBGAUTHSTATUS_EL1 RO
0x000000AA
32 Debug Authentication Status Register
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
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