B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
The ID_MMFR0_EL1 provides information about the memory model and memory management support
in AArch32.
Bit field descriptions
ID_MMFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 0
OuterShr PMSA
4 328 27 24 23 20 19 16 15
FCSE AuxReg TCM ShareLvl VMSAInnerShr
Figure B2-56 ID_MMFR0_EL1 bit assignments
InnerShr, [31:28]
Indicates the innermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
FCSE, [27:24]
Indicates support for Fast Context Switch Extension (FCSE):
0x0 Not supported.
AuxReg, [23:20]
Indicates support for Auxiliary registers:
0x2 Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary
Control Register.
TCM, [19:16]
Indicates support for TCMs and associated DMAs:
0x0 Not supported.
ShareLvl, [15:12]
Indicates the number of shareability levels implemented:
0x1 Two levels of shareability implemented.
OuterShr, [11:8]
Indicates the outermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
PMSA, [7:4]
Indicates support for a Protected Memory System Architecture (PMSA):
0x0 Not supported.
VMSA, [3:0]
Indicates support for a Virtual Memory System Architecture (VMSA).
B2 AArch64 system registers
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-246
Non-Confidential
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