ARM Cortex-A76 Core User Manual

B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
The ID_MMFR0_EL1 provides information about the memory model and memory management support
in AArch32.
Bit field descriptions
ID_MMFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 0
OuterShr PMSA
4 328 27 24 23 20 19 16 15
FCSE AuxReg TCM ShareLvl VMSAInnerShr
Figure B2-56 ID_MMFR0_EL1 bit assignments
InnerShr, [31:28]
Indicates the innermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
FCSE, [27:24]
Indicates support for Fast Context Switch Extension (FCSE):
0x0 Not supported.
AuxReg, [23:20]
Indicates support for Auxiliary registers:
0x2 Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary
Control Register.
TCM, [19:16]
Indicates support for TCMs and associated DMAs:
0x0 Not supported.
ShareLvl, [15:12]
Indicates the number of shareability levels implemented:
0x1 Two levels of shareability implemented.
OuterShr, [11:8]
Indicates the outermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
PMSA, [7:4]
Indicates support for a Protected Memory System Architecture (PMSA):
0x0 Not supported.
VMSA, [3:0]
Indicates support for a Virtual Memory System Architecture (VMSA).
B2 AArch64 system registers
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
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reserved.
B2-246
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core