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B2.93 TCR_EL1, Translation Control Register, EL1

The TCR_EL1 determines which Translation Base registers define the base address register for a

translation table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds

cacheability and shareability information.

Bit field descriptions

TCR_EL1 is a 64-bit register, and is part of the Virtual memory control registers functional group.

63 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35

IPS

34 32

HWU162

HWU161

HWU160

HWU159

HWU062

HWU061

HWU060

HWU059

HPD1

HPD0

TBI1

TBI0

TG1

31 30

SH1

29 28 27 26 25 24 23

T1SZ

21 16

TG0

15 14

SH0

13 12 11 10 9 8 7 6

T0SZ

5 0

ORGN1

IRGN1

EPD ORGN0

IRGN0

EPD

RES0

Figure B2-77 TCR_EL1 bit assignments

Note

Bits[50:39], architecturally defined, are implemented in the core.

HD, [40]

Hardware management of dirty state in stage 1 translations from EL0 and EL1. The possible

values are:

0 Stage 1 hardware management of dirty state disabled.

1 Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

HA, [39]

Hardware Access flag update in stage 1 translations from EL0 and EL1. The possible values are:

0 Stage 1 Access flag update disabled.

1 Stage 1 Access flag update enabled.

Configurations

RW fields in this register reset to UNKNOWN values.

Bit fields and details that are not provided in this description are architecturally defined. See the

Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.93 TCR_EL1, Translation Control Register, EL1

reserved.

B2-278

Non-Confidential

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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core