ARM Cortex-A76 Core

B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
The ID_ISAR2_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
MultiAccessInt
Reversal PSR_AR MultU MultS Mult MemHint LoadStore
Figure B2-51 ID_ISAR2_EL1 bit assignments
Reversal, [31:28]
Indicates the implemented Reversal instructions:
0x2 The REV, REV16, REVSH, and RBIT instructions.
PSR_AR, [27:24]
Indicates the implemented A and R profile instructions to manipulate the PSR:
0x1 The MRS and MSR instructions, and the exception return forms of data-processing
instructions.
The exception return forms of the data-processing instructions are:
• In the A32 instruction set, data-processing instructions with the PC as the destination and the
S bit set.
• In the T32 instruction set, the SUBSPC, LR, #N instruction.
MultU, [23:20]
Indicates the implemented advanced unsigned Multiply instructions:
0x2 The UMULL, UMLAL, and UMAAL instructions.
MultS, [19:16]
Indicates the implemented advanced signed Multiply instructions.
0x3 • The SMULL and SMLAL instructions.
• The SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT,
SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions,
and the Q bit in the PSRs.
• The SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA,
SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX
instructions.
Mult, [15:12]
Indicates the implemented additional Multiply instructions:
0x2 The MUL, MLA and MLS instructions.
MultiAccessInt, [11:8]
Indicates the support for interruptible multi-access instructions:
B2 AArch64 system registers
B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
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B2-237
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