ARM Cortex-A76 Core User Manual

B4.12 AArch64 virtual GIC CPU interface register summary
The following table describes the AArch64 virtual GIC CPU interface system registers that have
IMPLEMENTATION DEFINED bits.
See the Arm
®
Generic Interrupt Controller Architecture Specification for more information and a
complete list of AArch64 virtual GIC CPU interface system registers.
Table B4-3 AArch64 virtual GIC CPU interface register summary
Name Op0 Op1 CRn CRm Op2 Type Description
ICV_AP0R0_EL1 3 0 12 8 4 RW B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities
Group 0 Register 0, EL1 on page B4-329
ICV_AP1R0_EL1 3 0 12 9 0 RW B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities
Group 1 Register 0, EL1 on page B4-330
ICV_BRP0_EL1 3 0 12 8 3 RW B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point
Register 0, EL1 on page B4-331
ICV_BPR1_EL1 3 0 12 12 3 RW B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point
Register 1, EL1 on page B4-332
ICV_CTLR_EL1 3 0 12 12 4 RW B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register,
EL1 on page B4-333
B4 GIC registers
B4.12 AArch64 virtual GIC CPU interface register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-328
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core