ARM Cortex-A76 Core User Manual

B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
The ID_ISAR5_EL1 provides information about the instruction sets that the core implements.
Bit field descriptions
ID_ISAR5_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
RDM
31 12 11 8 7 0
SHA1 AES SEVLSHA2
4 316 1520 19
CRC32
23242728
RES0
Figure B2-54 ID_ISAR5_EL1 bit assignments
[31:28]
RES0 Reserved.
RDM, [27:24]
VQRDMLAH and VQRDMLSH instructions in AArch32. The value is:
0x1 VQRDMLAH and VQRDMLSH instructions are implemented.
[23:20]
RES0 Reserved.
CRC32, [19:16]
Indicates whether CRC32 instructions are implemented in AArch32 state. The value is:
0x1 CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions are
implemented.
SHA2, [15:12]
Indicates whether SHA2 instructions are implemented in AArch32 state. The possible values
are:
0x0 No SHA2 instructions implemented. This is the value when the Cryptographic
Extensions are not implemented or are disabled.
0x1 SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented. This is
the value when the Cryptographic Extensions are implemented and enabled.
SHA1, [11:8]
Indicates whether SHA1 instructions are implemented in AArch32 state. The possible values
are:
0x0 No SHA1 instructions implemented. This is the value when the Cryptographic
Extensions are not implemented or are disabled.
0x1 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.
This is the value when the Cryptographic Extensions are implemented and enabled.
AES, [7:4]
B2 AArch64 system registers
B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
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B2-243
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core