ARM Cortex-A76 Core User Manual

D9.34 TRCIDR5, ID Register 5
The TRCIDR5 returns how many resources the trace unit supports.
Bit field descriptions
31 025 24 16 15 82728
NUMEXTINTRACEIDSIZE
NUMEXTINSEL
91112
ATBTRIG
30 23 22 21
LPOVERRIDE
NUMSEQSTATE
NUMCNTR
REDFUNCNTR
RES0
Figure D9-32 TRCIDR5 bit assignments
REDFUNCNTR, [31]
Reduced Function Counter implemented:
0 Reduced Function Counter not implemented.
NUMCNTR, [30:28]
Number of counters implemented:
0b010 Two counters implemented.
NUMSEQSTATE, [27:25]
Number of sequencer states implemented:
0b100 Four sequencer states implemented.
RES0, [24]
RES0 Reserved.
LPOVERRIDE, [23]
Low-power state override support:
1 Low-power state override support implemented.
ATBTRIG, [22]
ATB trigger support:
1 ATB trigger support implemented.
TRACEIDSIZE, [21:16]
Number of bits of trace ID:
0x07 Seven-bit trace ID implemented.
RES0, [15:12]
RES0 Reserved.
NUMEXTINSEL, [11:9]
D9 ETM registers
D9.34 TRCIDR5, ID Register 5
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D9-543
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core