ARM Cortex-A76 Core User Manual

D6.1 Memory-mapped PMU register summary
There are PMU registers that are accessible through the external debug interface.
These registers are listed in the following table. For those registers not described in this chapter, see the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Table D6-1 Memory-mapped PMU register summary
Offset Name Type Description
0x000
PMEVCNTR0_EL0 RW
Performance Monitor Event Count Register
0
0x004
- - Reserved
0x008
PMEVCNTR1_EL0 RW
Performance Monitor Event Count Register
1
0x00C
- - Reserved
0x010
PMEVCNTR2_EL0 RW
Performance Monitor Event Count Register
2
0x014
- - Reserved
0x018
PMEVCNTR3_EL0 RW
Performance Monitor Event Count Register
3
0x01C
- - Reserved
0x020
PMEVCNTR4_EL0 RW
Performance Monitor Event Count Register
4
0x024
- - Reserved
0x028
PMEVCNTR5_EL0 RW
Performance Monitor Event Count Register
5
0x02C-0xF4
- - Reserved
0x0F8
PMCCNTR_EL0[31:0] RW
Performance Monitor Cycle Count Register
0x0FC
PMCCNTR_EL0[63:32] RW
0x200
PMPCSR[31:0] RO
Program Counter Sample Register
0x204
PMPCSR[63:32]
0x208
PMCID1SR RO
CONTEXTIDR_EL1 Sample Register
0x20C
PMVIDSR RO VMID Sample Register
0x220
PMPCSR[31:0] RO
Program Counter Sample Register (alias)
0x224
PMPCSR[63:32]
0x228
PMCID1SR RO
CONTEXTIDR_EL1 Sample Register
(alias)
0x22C
PMCID2SR RO CONTEXTIDR_EL2 Sample Register
0x100-0x3FC
- - Reserved
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core