ARM Cortex-A76 Core User Manual

C3.1 About the AMU
The Cortex-A76 core includes activity monitoring. It has features in common with performance
monitoring, but is intended for system management use whereas performance monitoring is aimed at
user and debug applications.
The activity monitors provide useful information for system power management and persistent
monitoring. The activity monitors are read-only in operation and their configuration is limited to the
highest Exception level implemented.
The Cortex-A76 core implements five counters, 0-4, and activity monitoring is only implemented in
AArch64.
C3 Activity Monitor Unit
C3.1 About the AMU
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
C3-386
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core