ARM Cortex-A76 Core User Manual

A4.6 Core power modes
The following figure shows the supported modes for each core domain P-Channel, and the legal
transitions between them.
Off
Off
(Emulated)
Debug
Recovery
On
Dynamic
retention
From any
power mode
Figure A4-4 Cortex-A76 core power domain mode transitions
The blue modes indicate the modes the channel can be initialized into.
A4.6.1 On
In this mode, the core is on and fully operational.
The core can be initialized into the On mode. If the core does not use P-Channel, you can tie the core in
the On mode by tying PREQ LOW.
When a transition to the On mode completes, all caches are accessible and coherent. Other than the
normal architectural steps to enable caches, no additional software configuration is required.
When the core domain P-Channel is initialized into the On mode, either as a shortcut for entering that
mode or as a tie-off for an unused P-Channel, it is an assumed transition from the Off mode. This
includes an invalidation of any cache RAM within the core domain.
A4.6.2 Off
The Cortex-A76 core supports a full shutdown mode where power can be removed completely and no
state is retained.
The shutdown can be for either the whole cluster or just for an individual core, which allows other cores
in the cluster to continue operating.
In this mode, all core logic and RAMs are off. The domain is inoperable and all core state is lost. The L1
and L2 caches are disabled, flushed and the core is removed from coherency automatically on transition
to Off mode.
A Cold reset can reset the core in this mode.
The core P-Channel can be initialized into this mode.
An attempted debug access when the core domain is off returns an error response on the internal debug
interface indicating the core is not available.
A4 Power management
A4.6 Core power modes
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core