A6.1 About the L1 memory system
The Cortex-A76 L1 memory system is designed to enhance core performance and save power.
The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
A6.1.1 L1 instruction-side memory system
The L1 instruction memory system has the following key features:
• Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, Physically
Tagged (PIPT) 4-way set-associative L1 data cache.
• Fixed cache line length of 64 bytes.
• Pseudo-LRU cache replacement policy.
• 256-bit read interface from the L2 memory system.
A6.1.2 L1 data-side memory system
The L1 data memory system has the following features:
• Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, Physically
Tagged (PIPT) 4-way set-associative L1 data cache.
• Fixed cache line length of 64 bytes.
• Pseudo-LRU cache replacement policy.
• 256-bit write interface to the L2 memory system.
• 256-bit read interface from the L2 memory system.
• Two 128-bit read paths from the data L1 memory system to the datapath.
• 256-bit write path from the datapath to the L1 memory system.
A6 Level 1 memory system
A6.1 About the L1 memory system
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