ARM Cortex-A76 Core User Manual

D9.43 TRCITCTRL, Integration Mode Control Register
The TRCITCTRL enables topology detection or integration testing, by putting the ETM trace unit into
integration mode.
Bit field descriptions
The TRCITCTRL is a 32-bit register.
31 0
IME
1
RES0
Figure D9-41 TRCITCTRL bit assignments
RES0, [31:1]
RES0 Reserved.
IME, [0]
Integration mode enable bit. The possible values are:
0 The trace unit is not in integration mode.
1 The trace unit is in integration mode. This mode enables:
• A debug agent to perform topology detection.
• SoC test software to perform integration testing.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITCTRL can be accessed through the external debug interface, offset 0xF00.
D9 ETM registers
D9.43 TRCITCTRL, Integration Mode Control Register
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D9-553
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core