D9.43 TRCITCTRL, Integration Mode Control Register
The TRCITCTRL enables topology detection or integration testing, by putting the ETM trace unit into
integration mode.
Bit field descriptions
The TRCITCTRL is a 32-bit register.
31 0
IME
1
RES0
Figure D9-41 TRCITCTRL bit assignments
RES0, [31:1]
RES0 Reserved.
IME, [0]
Integration mode enable bit. The possible values are:
0 The trace unit is not in integration mode.
1 The trace unit is in integration mode. This mode enables:
• A debug agent to perform topology detection.
• SoC test software to perform integration testing.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITCTRL can be accessed through the external debug interface, offset 0xF00.
D9 ETM registers
D9.43 TRCITCTRL, Integration Mode Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-553
Non-Confidential
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