D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
The TRCVISSCTLR defines the single address comparators that control the ViewInst Start/Stop logic.
Bit field descriptions
The TRCVISSCTLR is a 32-bit register.
31 0
STOP
16 15 8
START
2324 7
RES0
Figure D9-71 TRCVISSCTLR bit assignments
RES0, [31:24]
RES0 Reserved.
STOP, [23:16]
Defines the single address comparators to stop trace with the ViewInst Start/Stop control.
One bit is provided for each implemented single address comparator.
RES0, [15:8]
RES0 Reserved.
START, [7:0]
Defines the single address comparators to start trace with the ViewInst Start/Stop control.
One bit is provided for each implemented single address comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCVISSCTLR can be accessed through the external debug interface, offset 0x088.
D9 ETM registers
D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-586
Non-Confidential
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