ARM Cortex-A76 Core User Manual

B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
The ID_AA64MMFR1_EL1 provides information about the implemented memory model and memory
management support in the AArch64 Execution state.
Bit field descriptions
ID_AA64MMFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
SpecSEI
63 04 38 712 1116 15
VH VMID
20 19
HDPAN HAFDBS
24 2328 27
XNX
32 31
LO
RES0
Figure B2-43 ID_AA64MMFR1_EL1 bit assignments
RES0, [63:32]
RES0 Reserved.
XNX, [31:28]
Indicates whether provision of EL0 vs EL1 execute never control at Stage 2 is supported.
0x1 EL0/EL1 execute control distinction at Stage 2 bit is supported. All other values are
reserved.
SpecSEI, [27:24]
Describes whether the PE can generate SError interrupt exceptions from speculative reads of
memory, including speculative instruction fetches.
0x0 The PE never generates an SError interrupt due to an external abort on a speculative
read.
PAN, [23:20]
Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2,
SPSR_EL3, and DSPSR_EL0.
0x2 PAN supported and AT S1E1RP and AT S1E1WP instructions supported.
LO, [19:16]
Indicates support for LORegions.
0x1
LORegions are supported.
HD, [15:12]
Presence of Hierarchical Disables. Enables an operating system or hypervisor to hand over up to
4 bits of the last level page table descriptor (bits[62:59] of the page table entry) for use by
hardware for IMPLEMENTATION DEFINED usage. The value is:
0x2 Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported.
VH, [11:8]
Indicates whether Virtualization Host Extensions are supported.
B2 AArch64 system registers
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core