ARM Cortex-A76 Core User Manual

B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
The CCSIDR_EL1 provides information about the architecture of the currently selected cache.
Bit field descriptions
CCSIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
WB
31 28 27 12 3 0
RA
LineSizeWT
30 29 13 2
WA
NumSets Associativity
Figure B2-14 CCSIDR_EL1 bit assignments
WT, [31]
Indicates whether the selected cache level supports Write-Through:
0 Cache Write-Through is not supported at any level.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
WB, [30]
Indicates whether the selected cache level supports Write-Back. Permitted values are:
0 Write-Back is not supported.
1 Write-Back is supported.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
RA, [29]
Indicates whether the selected cache level supports read-allocation. Permitted values are:
0 Read-allocation is not supported.
1 Read-allocation is supported.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
WA, [28]
Indicates whether the selected cache level supports write-allocation. Permitted values are:
0 Write-allocation is not supported.
1 Write-allocation is supported.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
NumSets, [27:13]
(Number of sets in cache) - 1. Therefore, a value of 0 indicates one set in the cache. The number
of sets does not have to be a power of 2.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
B2 AArch64 system registers
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
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B2-159
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core