ARM Cortex-A76 Core User Manual

Associativity, [12:3]
(Associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
LineSize, [2:0]
(Log
2
(Number of bytes in cache line)) - 4. For example:
Indicates the (log
2
(number of words in cache line)) - 2:
For a line length of 16 bytes: Log
2
(16) = 4, LineSize entry = 0. This is the minimum
line length.
For a line length of 32 bytes: Log
2
(32) = 5, LineSize entry = 1.
For more information about encoding, see CCSIDR_EL1 encodings on page B2-160.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
CCSIDR_EL1 encodings
The following table shows the individual bit field and complete register encodings for the CCSIDR_EL1.
Table B2-6 CCSIDR encodings
CSSELR Cache Size Complete
register
encoding
Register bit field encoding
Level InD WT WB RA WA NumSets Associativity LineSize
0b000 0b0
L1 Data cache 64KB
701FE01A 0 1 1 1 0x00FF 0x003 2
0b000 0b1
L1 Instruction
cache
64KB
201FE01A 0 0 1 0 0x00FF 0x003 2
0b001 0b0
L2 cache 128KB
701FE03A 0 1 1 1 0x00FF 0x007 2
256KB
703FE03A 0 1 1 1 0x01FF 0x007 2
512KB
707FE03A 0 1 1 1 0x03FF 0x007 2
0b001 0b1
Reserved - - - - - - - - -
0b010 0b0
Reserved - - - - - - - - -
0b010 0b1
Reserved - - - - - - - - -
0b0101 - 0b1111 Reserved - - - - - - - - -
B2 AArch64 system registers
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-160
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core