ARM Cortex-A76 Core User Manual

B2.3 AArch64 implementation defined register summary
This section describes the AArch64 registers in the Cortex-A76 core that are implementation defined.
The following tables lists the AArch 64 implementation defined registers, sorted by opcode.
Table B2-3 AArch64 implementation defined registers
Name Copro CRn Op1 CRm Op2 Width Description
ATCR_EL1 3 c15 0 c7 0 32 Auxiliary Translation Control Register EL1
ATCR_EL2 3 c15 4 c7 0 32 Auxiliary Translation Control Register EL2
ATCR_EL12 3 c15 5 c7 0 32 Auxiliary Translation Control Register EL1
ATCR_EL3 3 c15 6 c7 0 32 Auxiliary Translation Control Register EL3
AVTCR_EL2 3 c15 4 c7 1 32 Auxiliary Virtualization Translation Control Register EL2
CPUACTLR_EL1 3 c15 0 c1 0 64 B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
on page B2-166
CPUACTLR2_EL1 3 c15 0 c1 1 64 B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2,
EL1 on page B2-168
CPUCFR_EL1 3 c15 0 c0 0 32 B2.25 CPUCFR_EL1, CPU Configuration Register, EL1
on page B2-170
CPUECTLR_EL1 3 c15 0 c1 4 64 B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
on page B2-172
CPUPCR_EL3 3 c15 6 c8 1 64 B2.27 CPUPCR_EL3, CPU Private Control Register, EL3
on page B2-180
CPUPMR_EL3 3 c15 6 c8 3 64 B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3
on page B2-182
CPUPOR_EL3 3 c15 6 c8 2 64 B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3
on page B2-184
CPUPSELR_EL3 3 c15 6 c8 0 32 B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3
on page B2-186
CPUPWRCTLR_EL1 3 c15 0 c2 7 32 B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
on page B2-188
ERXPFGCDNR_EL1 3 c15 0 c2 2 32 B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault
Generation Count Down Register, EL1 on page B2-203
ERXPFGCTLR_EL1 3 c15 0 c2 1 32 B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault
Generation Control Register, EL1 on page B2-204
ERXPFGFR_EL1 3 c15 0 c2 0 32 B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation
Feature Register, EL1 on page B2-206
The following table shows the 32-bit wide implementation defined Cluster registers. Details of these
registers can be found in Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual
B2 AArch64 system registers
B2.3 AArch64 implementation defined register summary
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core