ARM Cortex-A76 Core User Manual

B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
Register ERXSTATUS_EL1 accesses the ERR<n>STATUS primary status register for the error record
selected by ERRSELR_EL1.SEL.
If ERRSELR_EL1.SEL==0, then ERXSTATUS_EL1 accesses the ERR0STATUS register of the core
error record. See B3.10 ERR0STATUS, Error Record Primary Status Register on page B3-307.
If ERRSELR_EL1.SEL==1, then ERXSTATUS_EL1 accesses the ERR1STATUS register of the DSU
error record. See the Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual.
B2 AArch64 system registers
B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
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B2-207
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core