ARM Cortex-A76 Core

D9.41 TRCIMSPEC0, Implementation Specific Register 0
The TRCIMSPEC0 shows the presence of any implementation specific features, and enables any features
that are provided.
Bit field descriptions
The TRCIMSPEC0 is a 32-bit register.
31 0
4
SUPPORT
3
RES0
Figure D9-39 TRCIMSPEC0 bit assignments
RES0, [31:4]
RES0 Reserved.
SUPPORT, [3:0]
0 No implementation specific extensions are supported.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIMSPEC0 can be accessed through the external debug interface, offset 0x1C0.
D9 ETM registers
D9.41 TRCIMSPEC0, Implementation Specific Register 0
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D9-551
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