ARM Cortex-A76 Core User Manual

D9.15 TRCCLAIMSET, Claim Tag Set Register
The TRCCLAIMSET sets bits in the claim tag and determines the number of claim tag bits implemented.
Bit field descriptions
The TRCCLAIMSET is a 32-bit register.
31 4 3 0
SET
RES0
Figure D9-14 TRCCLAIMSET bit assignments
RES0, [31:4]
RES0 Reserved.
SET, [3:0]
On reads, for each bit:
0 Claim tag bit is not implemented.
1 Claim tag bit is implemented.
On writes, for each bit:
0 Has no effect.
1 Sets the relevant bit of the claim tag.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCLAIMSET can be accessed through the external debug interface, offset 0xFA0.
D9 ETM registers
D9.15 TRCCLAIMSET, Claim Tag Set Register
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D9-514
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core