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C2.2 PMU functional description

This section describes the functionality of the PMU.

The PMU includes the following interfaces and counters:

Event interface

Events from all other units from across the design are provided to the PMU.

System register and APB interface

You can program the PMU registers using the system registers or the external APB interface.

Counters

The PMU has 32-bit counters that increment when they are enabled, based on events, and a 64-

bit cycle counter.

PMU register interfaces

The Cortex-A76 core supports access to the performance monitor registers from the internal

system register interface and a memory-mapped interface.

C2.2.1 External register access permissions

Whether or not access is permitted to a register depends on:

• If the core is powered up.

• The state of the OS Lock and OS Double Lock.

• The state of External Performance Monitors access disable.

• The state of the debug authentication inputs to the core.

The behavior is specific to each register and is not described in this document. For a detailed description

of these features and their effects on the registers, see the Arm

Architecture Reference Manual Arm

v8,

for Arm

v8-A architecture profile.

The register descriptions provided in this manual describe whether each register is read/write or read-

only.

C2 Performance Monitor Unit

C2.2 PMU functional description

reserved.

C2-373

Non-Confidential

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ARM Cortex-A76 Core Specifications

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