ARM Cortex-A76 Core User Manual

D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to
instruction addresses.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
31 30 3 2 1 0
STATUS DV
DA
INST
RES0
Figure D9-63 TRCSSCSR0 bit assignments
STATUS, [31]
Single-shot status. This indicates whether any of the selected comparators have matched:
0 Match has not occurred.
1 Match has occurred at least once.
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be
explicitly written to 0 to enable this single-shot comparator control.
RES0, [30:3]
RES0 Reserved.
DV, [2]
Data value comparator support:
0 Single-shot data value comparisons not supported.
DA, [1]
Data address comparator support:
0 Single-shot data address comparisons not supported.
INST, [0]
Instruction address comparator support:
1 Single-shot instruction address comparisons supported.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.
D9 ETM registers
D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
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D9-577
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core