D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to
instruction addresses.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
31 30 3 2 1 0
STATUS DV
DA
INST
RES0
Figure D9-63 TRCSSCSR0 bit assignments
STATUS, [31]
Single-shot status. This indicates whether any of the selected comparators have matched:
0 Match has not occurred.
1 Match has occurred at least once.
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be
explicitly written to 0 to enable this single-shot comparator control.
RES0, [30:3]
RES0 Reserved.
DV, [2]
Data value comparator support:
0 Single-shot data value comparisons not supported.
DA, [1]
Data address comparator support:
0 Single-shot data address comparisons not supported.
INST, [0]
Instruction address comparator support:
1 Single-shot instruction address comparisons supported.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.
D9 ETM registers
D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-577
Non-Confidential
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