ARM Cortex-A76 Core User Manual

C2.5 Exporting PMU events
Some of the PMU events are exported to the ETM trace unit to be monitored.
Note
The PMUEVENT bus is not exported to external components. This is because the event bus cannot
safely cross an asynchronous boundary when events can be generated on every cycle.
C2 Performance Monitor Unit
C2.5 Exporting PMU events
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C2-384
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core