ARM Cortex-A76 Core User Manual

D9.20 TRCCONFIGR, Trace Configuration Register
The TRCCONFIGR controls the tracing options.
Bit field descriptions
The TRCCONFIGR is a 32-bit register.
31 012 11 10 8 67 5 4 3 2
VMID
CID
CCI
BB
13 1
RES0
RES1
1415161718
QE COND
DV
DA
VMIDOPT
RS
TS
INSTP0
Figure D9-19 TRCCONFIGR bit assignments
RES0, [31:18]
RES0 Reserved.
DV, [17]
Enables data value tracing. The possible values are:
0 Disables data value tracing.
1 Enables data value tracing.
DA, [16]
Enables data address tracing. The possible values are:
0 Disables data address tracing.
1 Enables data address tracing.
VMIDOPT, [15]
Configures the Virtual context identifier value used by the trace unit, both for trace generation
and in the Virtual context identifier comparators. The possible values are:
0b0 VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context identifier
larger than the VTTBR_EL2.VMID, the upper unused bits are always zero. If the trace
unit supports a Virtual context identifier larger than 8 bits and if the VTCR_EL2.VS
bit forces use of an 8-bit Virtual context identifier, bits [15:8] of the trace unit Virtual
context identifier are always zero.
0b1 CONTEXTIDR_EL2 is used. TRCIDR2.VMIDOPT indicates whether this field is
implemented.
QE, [14:13]
Enables Q element. The possible values are:
0b00 Q elements are disabled.
0b01 Q elements with instruction counts are disabled. Q elements without instruction counts
are disabled.
0b10 Reserved.
0b11 Q elements with and without instruction counts are enabled.
D9 ETM registers
D9.20 TRCCONFIGR, Trace Configuration Register
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reserved.
D9-521
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core