ARM Cortex-A76 Core User Manual

RS, [12]
Enables the return stack. The possible values are:
0 Disables the return stack.
1 Enables the return stack.
TS, [11]
Enables global timestamp tracing. The possible values are:
0 Disables global timestamp tracing.
1 Enables global timestamp tracing.
COND, [10:8]
Enables conditional instruction tracing. The possible values are:
0b000 Conditional instruction tracing is disabled.
0b001 Conditional load instructions are traced.
0b010 Conditional store instructions are traced.
0b011 Conditional load and store instructions are traced.
0b111 All conditional instructions are traced.
VMID, [7]
Enables VMID tracing. The possible values are:
0 Disables VMID tracing.
1 Enables VMID tracing.
CID, [6]
Enables context ID tracing. The possible values are:
0 Disables context ID tracing.
1 Enables context ID tracing.
RES0, [5]
RES0 Reserved.
CCI, [4]
Enables cycle counting instruction trace. The possible values are:
0 Disables cycle counting instruction trace.
1 Enables cycle counting instruction trace.
BB, [3]
Enables branch broadcast mode. The possible values are:
0 Disables branch broadcast mode.
1 Enables branch broadcast mode.
INSTP0, [2:1]
Controls whether load and store instructions are traced as P0 instructions. The possible values
are:
0b00 Load and store instructions are not traced as P0 instructions.
0b01 Load instructions are traced as P0 instructions.
D9 ETM registers
D9.20 TRCCONFIGR, Trace Configuration Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-522
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core