B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
AFSR0_EL3 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are
taken to EL3. In the Cortex-A76 core, no additional information is provided for these exceptions.
Therefore this register is not used.
Bit field descriptions
AFSR0_EL3 is a 32-bit register, and is part of:
• The Exception and fault handling registers functional group.
• The Security registers functional group.
• The IMPLEMENTATION DEFINED functional group.
031
RES0
Figure B2-6 AFSR0_EL3 bit assignments
RES0, [31:0]
Reserved, RES0.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-151
Non-Confidential
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