D8.1 AArch64 AMU register summary
The following table gives a summary of the Cortex-A76 AMU registers in the AArch64 Execution state.
Table D8-1 AArch64 AMU registers
Name Width Reset Description
AMCNTENCLR_EL0 32
0x00000000
D8.2 AMCNTENCLR0_EL0, Activity Monitors Count
Enable Clear Register, EL0 on page D8-483
AMCNTENSET_EL0 32
0x00000000
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable
Set Register, EL0 on page D8-484
AMCFGR_EL0 32
0x00003F04
D8.4 AMCFGR_EL0, Activity Monitors Configuration
Register, EL0 on page D8-485
AMUSERENR_EL0 32
0x00000000
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable
access, EL0 on page D8-487
AMEVCNTRn_EL0 64
0x0000000000000000
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter
Register, EL0 on page D8-489
AMEVTYPERn_EL0 32 The reset value depends on the
register:
• AMEVTYPER0_EL0 =
0x00000011.
• AMEVTYPER1_EL0 =
0x000000EF.
• AMEVTYPER2_EL0 =
0x00000008.
• AMEVTYPER3_EL0 =
0x000000F0.
• AMEVTYPER4_EL0 =
0x000000F1.
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type
Register, EL0 on page D8-490
D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D8-482
Non-Confidential
To Next Page
Loading...
