ARM Cortex-A76 Core User Manual

D8.1 AArch64 AMU register summary
The following table gives a summary of the Cortex-A76 AMU registers in the AArch64 Execution state.
Table D8-1 AArch64 AMU registers
Name Width Reset Description
AMCNTENCLR_EL0 32
0x00000000
D8.2 AMCNTENCLR0_EL0, Activity Monitors Count
Enable Clear Register, EL0 on page D8-483
AMCNTENSET_EL0 32
0x00000000
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable
Set Register, EL0 on page D8-484
AMCFGR_EL0 32
0x00003F04
D8.4 AMCFGR_EL0, Activity Monitors Configuration
Register, EL0 on page D8-485
AMUSERENR_EL0 32
0x00000000
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable
access, EL0 on page D8-487
AMEVCNTRn_EL0 64
0x0000000000000000
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter
Register, EL0 on page D8-489
AMEVTYPERn_EL0 32 The reset value depends on the
register:
• AMEVTYPER0_EL0 =
0x00000011.
• AMEVTYPER1_EL0 =
0x000000EF.
• AMEVTYPER2_EL0 =
0x00000008.
• AMEVTYPER3_EL0 =
0x000000F0.
• AMEVTYPER4_EL0 =
0x000000F1.
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type
Register, EL0 on page D8-490
D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary
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D8-482
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core