ARM Cortex-A76 Core User Manual

D7.9 PMSSCR, PMU Snapshot Capture Register
The PMSSCR provides a mechanism for software to initiate a sample.
Bit field descriptions
The PMSSCR is a 32-bit write-only register.
31 0
1
RES0
SS
Figure D7-3 PMSSCR bit assignments
RES0, [31:1]
Reserved, RES0.
SS, [0]
Capture now. The possible values are:
0 Ignored.
1 Initiate a capture immediately.
Configurations
There are no configuration notes.
Usage constraints
Any access to PMSSCR returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
D7 PMU snapshot registers
D7.9 PMSSCR, PMU Snapshot Capture Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core