B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
ICC_SRE_EL2 controls whether the system register interface or the memory-mapped interface to the
GIC CPU interface is used for EL2.
Bit field descriptions
ICC_SRE_EL2 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Virtualization registers functional group.
• The GIC control registers functional group.
31
0
12
3
SRE
DFB
DIB
RES0
4
Enable
Figure B4-6 ICC_SRE_EL2 bit assignments
RES0, [31:4]
Reserved, RES0.
Enable, [3]
Enables lower Exception level access to ICC_SRE_EL1. The value is:
0x1 Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL2.
This bit is RAO/WI.
DIB, [2]
Disable IRQ bypass. The possible values are:
0x0 IRQ bypass enabled.
0x1 IRQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DIB
DFB, [1]
Disable FIQ bypass. The possible values are:
0x0 FIQ bypass enabled.
0x1 FIQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DFB
SRE, [0]
System Register Enable. The value is:
0x1 The System register interface for the current Security state is enabled.
B4 GIC registers
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
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reserved.
B4-324
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