B2.94 TCR_EL2, Translation Control Register, EL2
The TCR_EL2 controls translation table walks required for stage 1 translation of a memory access from
EL2 and holds cacheability and shareability information.
Bit field descriptions
TCR_EL2 is a 32-bit register.
TCR_EL2 is part of:
• The Virtual memory control registers functional group.
• The Hypervisor and virtualization registers functional group.
31 30 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5
0
SH0TG0PS
IRGN0
ORGN0
T0SZ
TBI
HA
HD
HPD
252829
HWU62-59
RES0
RES1
Figure B2-78 TCR_EL2 bit assignments
Note
Bits[28:21], architecturally defined, are implemented in the core.
HD, [22]
Dirty bit update. The possible values are:
0 Dirty bit update is disabled.
1 Dirty bit update is enabled.
HA, [21]
Stage 1 Access flag update. The possible values are:
0 Stage 1 Access flag update is enabled.
1 Stage 1 Access flag update is disabled.
Configurations
When the Virtualization Host Extension is activated, TCR_EL2 has the same bit assignments as
TCR_EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.94 TCR_EL2, Translation Control Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-279
Non-Confidential
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