ARM Cortex-A76 Core User Manual

B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
The ID_AA64ISAR0_EL1 provides information about the instructions implemented in AArch64 state,
including the instructions that are provided by the Cryptographic Extension.
Bit field descriptions
ID_AA64ISAR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
The optional Cryptographic Extension is not included in the base product of the core. Arm requires
licensees to have contractual rights to obtain the Cryptographic Extension.
63 0
AESSHA1SHA2
16 15 12 11 8 7 4 3
CRC32
20 1923
Atomic
27 242831
RDM
32
RES0
43444748
DP
Figure B2-40 ID_AA64ISAR0_EL1 bit assignments
RES0, [63:48]
RES0 Reserved.
DP, [47:44]
Indicates whether Dot Product support instructions are implemented.
0x1 UDOT, SDOT instructions are implemented.
RES0, [43:32]
RES0 Reserved.
RDM, [31:28]
Indicates whether SQRDMLAH and SQRDMLSH instructions in AArch64 are implemented.
0x1 SQRDMLAH and SQRDMLSH instructions implemented.
RES0, [27:24]
RES0 Reserved.
Atomic, [23:20]
Indicates whether Atomic instructions in AArch64 are implemented. The value is:
0x2 LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP
instructions are implemented
.
CRC32, [19:16]
Indicates whether CRC32 instructions are implemented. The value is:
0x1 CRC32 instructions are implemented.
SHA2, [15:12]
Indicates whether SHA2 instructions are implemented. The possible values are:
B2 AArch64 system registers
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
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B2-219
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core