ARM Cortex-A76 Core User Manual

B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
The ID_MMFR2_EL1 provides information about the implemented memory model and memory
management support in AArch32.
Bit field descriptions
ID_MMFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 0
HWAccFlg
4 328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG
Figure B2-58 ID_MMFR2_EL1 bit assignments
HWAccFlg, [31:28]
Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7
implementation:
0x0 Not supported.
WFIStall, [27:24]
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
0x1 Support for WFI stalling.
MemBarr, [23:20]
Memory Barrier. Indicates the supported CP15 memory barrier operations.
0x2 Supported CP15 memory barrier operations are:
• Data Synchronization Barrier (DSB).
• Instruction Synchronization Barrier (ISB).
• Data Memory Barrier (DMB).
UniTLB, [19:16]
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB
implementation.
0x6 Supported unified TLB maintenance operations are:
• Invalidate all entries in the TLB.
• Invalidate TLB entry by MVA.
• Invalidate TLB entries by ASID match.
• Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a
shared unified TLB operation.
• Invalidate Hyp mode unified TLB entry by MVA.
• Invalidate entire Non-secure EL1 and EL0 unified TLB.
• Invalidate entire Hyp mode unified TLB.
• TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.
• TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.
HvdTLB, [15:12]
Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB
implementation:
0x0 Not supported.
B2 AArch64 system registers
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core