B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
The ID_MMFR2_EL1 provides information about the implemented memory model and memory
management support in AArch32.
Bit field descriptions
ID_MMFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 0
HWAccFlg
4 328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG
Figure B2-58 ID_MMFR2_EL1 bit assignments
HWAccFlg, [31:28]
Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7
implementation:
0x0 Not supported.
WFIStall, [27:24]
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
0x1 Support for WFI stalling.
MemBarr, [23:20]
Memory Barrier. Indicates the supported CP15 memory barrier operations.
0x2 Supported CP15 memory barrier operations are:
• Data Synchronization Barrier (DSB).
• Instruction Synchronization Barrier (ISB).
• Data Memory Barrier (DMB).
UniTLB, [19:16]
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB
implementation.
0x6 Supported unified TLB maintenance operations are:
• Invalidate all entries in the TLB.
• Invalidate TLB entry by MVA.
• Invalidate TLB entries by ASID match.
• Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a
shared unified TLB operation.
• Invalidate Hyp mode unified TLB entry by MVA.
• Invalidate entire Non-secure EL1 and EL0 unified TLB.
• Invalidate entire Hyp mode unified TLB.
• TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.
• TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.
HvdTLB, [15:12]
Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB
implementation:
0x0 Not supported.
B2 AArch64 system registers
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-250
Non-Confidential
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