Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache
implementation:
0x0 None supported.
Configurations
Must be interpreted with ID_MMFR0_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, and
ID_MMFR4_EL1. See:
• B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 on page B2-246.
• B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 on page B2-250.
• B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page B2-252.
• B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-249
Non-Confidential
To Next Page
Loading...
