D9.51 TRCOSLSR, OS Lock Status Register
The TRCOSLSR returns the status of the OS Lock.
Bit field descriptions
The TRCOSLSR is a 32-bit register.
31 1 0
OSLM[1]
3 24
nTT
OSLK
OSLM[0]
RES0
Figure D9-49 TRCOSLSR bit assignments
RES0, [31:4]
RES0 Reserved.
OSLM[1], [3]
OS Lock model [1] bit. This bit is combined with OSLM[0] to form a two-bit field that indicates
the OS Lock model is implemented.
The value of this field is always 0b10, indicating that the OS Lock is implemented.
nTT, [2]
This bit is RAZ, that indicates that software must perform a 32-bit write to update the
TRCOSLAR.
OSLK, [1]
OS Lock status bit:
0 OS Lock is unlocked.
1 OS Lock is locked.
OSLM[0], [0]
OS Lock model [0] bit. This bit is combined with OSLM[1] to form a two-bit field that indicates
the OS Lock model is implemented.
The value of this field is always 0b10, indicating that the OS Lock is implemented.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCOSLSR can be accessed through the external debug interface, offset 0x304.
D9 ETM registers
D9.51 TRCOSLSR, OS Lock Status Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-561
Non-Confidential
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