ARM Cortex-A76 Core User Manual

D9.51 TRCOSLSR, OS Lock Status Register
The TRCOSLSR returns the status of the OS Lock.
Bit field descriptions
The TRCOSLSR is a 32-bit register.
31 1 0
OSLM[1]
3 24
nTT
OSLK
OSLM[0]
RES0
Figure D9-49 TRCOSLSR bit assignments
RES0, [31:4]
RES0 Reserved.
OSLM[1], [3]
OS Lock model [1] bit. This bit is combined with OSLM[0] to form a two-bit field that indicates
the OS Lock model is implemented.
The value of this field is always 0b10, indicating that the OS Lock is implemented.
nTT, [2]
This bit is RAZ, that indicates that software must perform a 32-bit write to update the
TRCOSLAR.
OSLK, [1]
OS Lock status bit:
0 OS Lock is unlocked.
1 OS Lock is locked.
OSLM[0], [0]
OS Lock model [0] bit. This bit is combined with OSLM[1] to form a two-bit field that indicates
the OS Lock model is implemented.
The value of this field is always 0b10, indicating that the OS Lock is implemented.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCOSLSR can be accessed through the external debug interface, offset 0x304.
D9 ETM registers
D9.51 TRCOSLSR, OS Lock Status Register
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D9-561
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core