A7.3 Support for memory types
The Cortex-A76 core simplifies the coherency logic by downgrading some memory types.
• Memory that is marked as both Inner Write-Back Cacheable and Outer Write-Back Cacheable is
cached in the L1 data cache and the L2 cache.
• Memory that is marked Inner Write-Through is downgraded to Non-cacheable.
• Memory that is marked Outer Write-Through or Outer Non-cacheable is downgraded to Non-
cacheable, even if the inner attributes are Write-Back cacheable.
The following table shows the transaction capabilities of the Cortex-A76 core. It lists the maximum
possible values for read, write, DVM issuing, and snoop capabilities of the private L2 cache.
Table A7-1 Cortex-A76 Transaction Capabilities
Attribute Value Description
Write issuing capability 22/34/46 Maximum number of outstanding write
transactions. Dependent on the configured
TQ size. (24/36/48)
Read issuing capability 22/34/46 Maximum number of outstanding read
transactions. Dependent on the configured
TQ size. (24/36/48)
Snoop acceptance capability 17/23/29 Maximum number of outstanding snoops
and stashes accepted. Dependent on the TQ
size. (24/36/48)
DVM issuing capability 22/34/46 Maximum number of outstanding DVMOp
transactions. Dependent on the configured
TQ size. (24/36/48)
A7 Level 2 memory system
A7.3 Support for memory types
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A7-100
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