ARM Cortex-A76 Core User Manual

A9.1 About the Generic Interrupt Controller CPU interface
The Cortex-A76 core implements the GIC CPU interface as described in the Arm Generic Interrupt
Controller Architecture Specification.
This interfaces with an external GICv3 or GICv4 distributor component within the cluster system and is
a resource for supporting and managing interrupts. The GIC CPU interface hosts registers to mask,
identify and control states of interrupts forwarded to that core. Each core in the cluster system has a GIC
CPU interface component and connects to a common external distributor component.
Note
This chapter describes only features that are specific to the Cortex-A76 core implementation. Additional
information specific to the cluster can be found in Arm
®
DynamIQ
™
Shared Unit Technical Reference
Manual.
The GICv4 architecture supports:
• Two security states.
• Interrupt virtualization.
• Software-generated Interrupts (SGIs).
• Message Based Interrupts.
• System register access for the CPU interface.
• Interrupt masking and prioritization.
• Cluster environments, including systems that contain more than eight cores.
• Wake-up events in power management environments.
The GIC includes interrupt grouping functionality that supports:
• Configuring each interrupt to belong to an interrupt group.
• Signaling Group 1 interrupts to the target core using either the IRQ or the FIQ exception request.
Group 1 interrupts can be Secure or Non-secure.
• Signaling Group 0 interrupts to the target core using the FIQ exception request only.
• A unified scheme for handling the priority of Group 0 and Group 1 interrupts.
This chapter describes only features that are specific to the Cortex-A76 core implementation.
Related references
Chapter B4 GIC registers on page B4-311
A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A9-112
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core