ARM Cortex-A76 Core User Manual

A10.2 Accessing the feature identification registers
Software can identify the Advanced SIMD and floating-point features using the feature identification
registers in the AArch64 Execution state only.
The Cortex-A76 core only supports AArch32 in EL0, therefore none of the feature identification
registers are accessible in the AArch32 Execution state.
You can access the feature identification registers in the AArch64 Execution state using the MRS
instruction, for example:
MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt
MRS <Xt>, MVFR0_EL1 ; Read MVFR0_EL1 into Xt
MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt
MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt
Table A10-1 AArch64 Advanced SIMD and scalar floating-point feature identification registers
Register name Description
ID_AA64PFR0_EL1
See B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 on page B2-227.
MVFR0_EL1 See B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1 on page B5-351.
MVFR1_EL1 See B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1 on page B5-353.
MVFR2_EL1 See B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1 on page B5-355.
A10 Advanced SIMD and floating-point support
A10.2 Accessing the feature identification registers
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core