ARM Cortex-A76 Core User Manual

B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1
The CPACR_EL1 controls access to trace functionality and access to registers associated with Advanced
SIMD and floating-point execution.
Bit field descriptions
CPACR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.
31 0
FPEN
19202122
RES0
28
TTA
Figure B2-16 CPACR_EL1 bit assignments
RES0, [31:29]
RES0 Reserved.
TTA, [28]
Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1, from
both Execution states. This bit is RES0. The core does not provide System Register access to
ETM control.
Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1
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B2-163
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core