A1.1 About the core
The Cortex-A76 core is a high-performance and low-power Arm product that implements the Armv8-A
architecture.
The Cortex-A76 core supports:
• The Armv8.2-A extension.
• The RAS extension.
• The Load acquire (LDAPR) instructions introduced in the Armv8.3-A extension
• The Dot Product instruction support introduced in the Armv8.4-A extension.
• The PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB,
PSSBB) instructions introduced in the Armv8.5-A extension.
The Cortex-A76 core has a Level 1 (L1) memory system and a private, integrated Level 2 (L2) cache. It
also includes a superscalar, variable-length, out-of-order pipeline.
The Cortex-A76 core is implemented inside the DynamIQ Shared Unit (DSU) cluster. For more
information, see the Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual.
The following figure shows an example of a configuration with four Cortex-A76 cores.
External memory interface
DSU
Interrupt interface
Power management and
clock control
DFT
CoreSight infrastructure
DynamIQ™ Cluster
Core 0
Core 1
Core 2
Core 3
Figure A1-1 Example Cortex-A76 configuration
A1 Introduction
A1.1 About the core
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A1-26
Non-Confidential
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