ARM Cortex-A76 Core User Manual

A1.1 About the core
The Cortex-A76 core is a high-performance and low-power Arm product that implements the Armv8-A
architecture.
The Cortex-A76 core supports:
• The Armv8.2-A extension.
• The RAS extension.
• The Load acquire (LDAPR) instructions introduced in the Armv8.3-A extension
• The Dot Product instruction support introduced in the Armv8.4-A extension.
• The PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB,
PSSBB) instructions introduced in the Armv8.5-A extension.
The Cortex-A76 core has a Level 1 (L1) memory system and a private, integrated Level 2 (L2) cache. It
also includes a superscalar, variable-length, out-of-order pipeline.
The Cortex-A76 core is implemented inside the DynamIQ Shared Unit (DSU) cluster. For more
information, see the Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual.
The following figure shows an example of a configuration with four Cortex-A76 cores.
External memory interface
DSU
Interrupt interface
Power management and
clock control
DFT
CoreSight infrastructure
DynamIQ™ Cluster
Core 0
Core 1
Core 2
Core 3
Figure A1-1 Example Cortex-A76 configuration
A1 Introduction
A1.1 About the core
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A1-26
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core