B2.2 AArch64 architectural system register summary
This section describes the AArch64 architectural system registers implemented in the Cortex-A76 core.
The section contains two tables:
Registers with implementation defined bit fields
This table identifies the architecturally defined registers in Cortex-A76 that have
implementation defined bit fields. The register descriptions for these registers only contain
information about the implementation defined bits.
See Table B2-1 Registers with implementation defined bit fields on page B2-127.
Other architecturally defined registers
This table identifies the other architecturally defined registers that are implemented in the
Cortex-A76 core. These registers are described in the Arm
®
Architecture Reference Manual
Armv8, for Armv8-A architecture profile.
See Other architecturally defined registers on page B2-131.
Table B2-1 Registers with implementation defined bit fields
Name Op0 CRn Op1 CRm Op2 Width Description
ACTLR_EL1 3 c1 0 c0 1 64 B2.5 ACTLR_EL1, Auxiliary Control Register, EL1
on page B2-144
ACTLR_EL2 3 c1 4 c0 1 64 B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
on page B2-145
ACTLR_EL3 3 c1 6 c0 1 64 B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
on page B2-147
AIDR_EL1 3 c0 1 c0 7 32 B2.14 AIDR_EL1, Auxiliary ID Register, EL1 on page B2-155
AFSR0_EL1 3 c5 0 c1 0 32 B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
on page B2-149
AFSR0_EL2 3 c5 4 c1 0 32 B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
on page B2-150
AFSR0_EL3 3 c5 6 c1 0 32 B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
on page B2-151
AFSR1_EL1 3 c5 0 c1 1 32 B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
on page B2-152
AFSR1_EL2 3 c5 4 c1 1 32 B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
on page B2-153
AFSR1_EL3 3 c5 6 c1 1 32 B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
on page B2-154
AMAIR_EL1 3 c10 0 c3 0 64 B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection
Register, EL1 on page B2-156
AMAIR_EL2 3 c10 4 c3 0 64 B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection
Register, EL2 on page B2-157
AMAIR_EL3 3 c10 6 c3 0 64 B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection
Register, EL3 on page B2-158
CCSIDR_EL1 3 c0 1 c0 0 32 B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
on page B2-159
B2 AArch64 system registers
B2.2 AArch64 architectural system register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-127
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