ARM Cortex-A76 Core User Manual

B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
The ID_AA64MMFR0_EL1 provides information about the implemented memory model and memory
management support in the AArch64 Execution state.
Bit field descriptions
ID_AA64MMFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
63 04 38 712 1116 15
BigEnd ASIDBits
20 19
SNSMemTGran16 PARange
24 23
BigEndEL0
RES0
27283132
TGran64TGran4
Figure B2-42 ID_AA64MMFR0_EL1 bit assignments
RES0, [63:32]
RES0 Reserved.
TGran4, [31:28]
Support for 4KB memory translation granule size:
0x0 4KB granule supported.
TGran64, [27:24]
Support for 64KB memory translation granule size:
0x0 64KB granule supported.
TGran16, [23:20]
Support for 16KB memory translation granule size:
0x1 Indicates that the 16KB granule is supported.
BigEndEL0, [19:16]
Mixed-endian support only at EL0.
0x0 No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value.
SNSMem, [15:12]
Secure versus Non-secure Memory distinction:
0x1 Supports a distinction between Secure and Non-secure Memory.
BigEnd, [11:8]
Mixed-endian configuration support:
0x1 Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be
configured.
ASIDBits, [7:4]
Number of ASID bits:
0x2 16 bits.
B2 AArch64 system registers
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
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B2-222
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core