ARM Cortex-A76 Core

D3.5 EDCIDR3, External Debug Component Identification Register 3
The EDCIDR3 provides information to identify an external debug component.
Bit field descriptions
The EDCIDR3 is a 32-bit register.
31 0
PRMBL_3
78
RES0
Figure D3-4 EDCIDR3 bit assignments
RES0, [31:8]
RES0 Reserved.
PRMBL_3, [7:0]
0xB1 Preamble byte 3.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The EDCIDR3 can be accessed through the external debug interface, offset 0xFFC.
D3 Memory-mapped debug registers
D3.5 EDCIDR3, External Debug Component Identification Register 3
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