D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
The AMCNTENSET_EL0 enables the activity monitor counters implemented, AMEVCNTRn (n is 0-4).
Bit field descriptions
The AMCNTENSET_EL0 is a 32-bit register.
P<n>, bit[n]
AMEVCNTRn enable bit. The possible values are:
0 When this bit is read, the activity counter n is disabled. When it is written, it has no
effect.
1 When this bit is read, the activity counter n is enabled. When it is written, it enables
the activity counter n.
Configurations
There are no configuration notes.
Usage constraints
Accessing the AMCNTENSET_EL0
To access the AMCNTENSET_EL0:
MRS <Xt>, AMCNTENSET_EL0 ; Read AMCNTENSET_EL0 into Xt
MSR AMCNTENSET_EL0, <Xt> ; Write <Xt> to AMCNTENSET_EL0
Register access is encoded as follows:
Table D8-3 AMCNTENSET_EL0 encoding
op0 op1 CRn CRm op2
11 011 1111 1001 110
The AMCNTENSET_EL0 can be accessed through the external debug interface, offset 0xC00.
In this case, it is read-only.
This register is accessible as follows:
EL0 EL1 EL2 EL3
RO RO RO RW
Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are
trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped
to EL3.
If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.
D8 AArch64 AMU registers
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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D8-484
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