ARM Cortex-A76 Core

D3.4 EDCIDR2, External Debug Component Identification Register 2
The EDCIDR2 provides information to identify an external debug component.
Bit field descriptions
The EDCIDR2 is a 32-bit register.
31 0
PRMBL_2
78
RES0
Figure D3-3 EDCIDR2 bit assignments
RES0, [31:8]
RES0 Reserved.
PRMBL_2, [7:0]
0x05 Preamble byte 2.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The EDCIDR2 can be accessed through the external debug interface, offset 0xFF8.
D3 Memory-mapped debug registers
D3.4 EDCIDR2, External Debug Component Identification Register 2
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