B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
The ID_PFR0_EL1 provides top-level information about the instruction sets supported by the core in
AArch32.
Bit field descriptions
ID_PFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 0
State2 State1
16 15 4 3
State0State3
28
RAS
27
RES0
1920
CSV2
Figure B2-61 ID_PFR0_EL1 bit assignments
RAS, [31:28]
RAS extension version. The value is:
0x1 Version 1 of the RAS extension is present.
RES0, [27:20]
RES0 Reserved.
CSV2, [19:16]
0x0 This device does not disclose whether branch targets trained in one context can affect
speculative execution in a different context.
0x1 Branch targets trained in one context cannot affect speculative execution in a different
hardware described context. This is the reset value.
State3, [15:12]
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
0x0 Core does not support the T32EE instruction set.
State2, [11:8]
Indicates support for Jazelle. This value is:
0x1 Core supports trivial implementation of Jazelle.
State1, [7:4]
Indicates support for T32 instruction set. This value is:
0x3 Core supports T32 encoding after the introduction of Thumb-2 technology, and for all
16-bit and 32-bit T32 basic instructions.
State0, [3:0]
Indicates support for A32 instruction set. This value is:
0x1 A32 instruction set implemented.
B2 AArch64 system registers
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-256
Non-Confidential
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